Test MP+dmb.sy+addr-data-rfi-addr-[fr-rf]

AArch64 MP+dmb.sy+addr-data-rfi-addr-[fr-rf]
"DMB.SYdWW Rfe DpAddrdR DpDatadW Rfi DpAddrdR FrLeave RfBack Fre"
Cycle=Rfi DpAddrdR FrLeave RfBack Fre DMB.SYdWW Rfe DpAddrdR DpDatadW
Relax=
Safe=Rfi Rfe Fre DMB.SYdWW DpAddrdR DpDatadW [FrLeave,RfBack]
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr Rf
Orig=DMB.SYdWW Rfe DpAddrdR DpDatadW Rfi DpAddrdR FrLeave RfBack Fre
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X4=z; 1:X6=a; 1:X10=x;
2:X1=x;
}
 P0          | P1                   | P2          ;
 MOV W0,#2   | LDR W0,[X1]          | MOV W0,#1   ;
 STR W0,[X1] | EOR W2,W0,W0         | STR W0,[X1] ;
 DMB SY      | LDR W3,[X4,W2,SXTW]  |             ;
 MOV W2,#1   | EOR W5,W3,W3         |             ;
 STR W2,[X3] | ADD W5,W5,#1         |             ;
             | STR W5,[X6]          |             ;
             | LDR W7,[X6]          |             ;
             | EOR W8,W7,W7         |             ;
             | LDR W9,[X10,W8,SXTW] |             ;
             | LDR W11,[X10]        |             ;
Observed
    y=1; x=2; a=1; 1:X9=2; 1:X7=1; 1:X11=1; 1:X0=1;
and y=1; x=2; a=1; 1:X9=2; 1:X7=1; 1:X11=0; 1:X0=1;
and y=1; x=1; a=1; 1:X9=2; 1:X7=1; 1:X11=0; 1:X0=1;
and y=1; x=1; a=1; 1:X9=1; 1:X7=1; 1:X11=0; 1:X0=1;